Steffen Tarnick's research works | Universität Potsdam, Potsdam and other places
PDF) A Closed-Loop Approach for Improving the Wellness of Low-Income Elders at Home Using Game Consoles
PDF) New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults
Dimitris Magos's research works | University of West Attica, Athens (TEIATH) and other places
PDF) Multimode scan: Test per clock BIST for IP cores
PDF) An adaptive BIST to detect multiple stuck-open faults in CMOS circuits
PDF) Moduli Set Selection and Cost Estimation for RNS-Based FIR Filter and Filter Bank Design
PDF) High-Level Test Synthesis for Delay Fault Testability
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
Education and Information Technologies | Home
IVML > People > Phivos Mylonas
PDF) Memory testing with a RISC microcontroller
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
Education and Information Technologies | Home
Latest Award Winners
PDF) Detection of Delay Faults in Memory Address Decoders
PDF) On the Generation of Functional Test Programs for the Cache Replacement Logic
PDF) On the generation of pseudo-deterministic two-patterns test sequence with LFSRs.
PDF) Modeling and Simulation of Efficient March Algorithm for Memory Testing
NiDS2022 (Novel & Intelligent Digital Systems) - ATHENS
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) Test pattern generation based on arithmetic operations
PDF) UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations
PDF) Symmetry Measure for Memory Test and Its Application in BIST Optimization
PDF) Accumulator-Based Weighted Pattern Generation.
Education and Information Technologies | Home
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) Efficient Test Compaction for Pseudo-Random Testing
